Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered interconnect structures, such as, for example, single or dual damascene wiring structures. Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate.
Copper (Cu)-based interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability as compared to aluminum (Al)-based interconnects. However as devices shrink, the wiring capacitance becomes an increasingly large percentage of the overall capacitance, resulting in increased signal delay, power consumption and noise. Therefore low k dielectrics (having a dielectric constant of less than silicon dioxide) are becoming more of the mainstream for 90 nm technology node and beyond.
Unfortunately, the effective dielectric constant of such interconnects is higher than that of the low k dielectric due to the presence of dielectric capping layers such as, for example, SiN or SiC, that are typically used to passivate the Cu surfaces.
Recently, it has been shown that the circuit delay can be reduced by using a self-aligned CoWP cap instead of a dielectric capping layer in such interconnect structures. See, for example, T. Ko et al. entitled “High Performance/Reliability Cu Interconnect with Selective CoWP Cap”, VLSI Symp. Proc. 2003, p. 109. The CoWP cap is formed selectively on Cu-containing features using electroless plating, the details of which, can be found, for example, in A. Kohn et al. entitled “Characterization of electroless deposited Co(W,P) thin films for encapsulation of copper metallization”, Mater. Sci. Eng. A, 302, 18 (2001) and C.-K Hu et al. entitled “Reduced Cu interface diffusion by CoWP surface coating” Microelec. Eng. 70, 406 (2003).
Despite the advances in using CoWP caps, it is still unclear whether a CoWP cap by itself (without an overlying dielectric cap) can provide an adequate barrier during oxidizing processes such as, for example, dielectric deposition and resist stripping. During the dielectric deposition of oxide-based dielectrics by plasma enhanced chemical vapor deposition, the CoWP cap is exposed to an oxidizing ambient at temperatures of from 350° to 400° C. Both Cu and Co are known to oxidize at low temperatures (e.g., less than 400° C.).
J. Gambino et al. “Thermal Oxidation of Cu interconnects capped with CoWP”, Materials, Technology, and Reliability of Advanced Interconnects-2005, MRS Proc., Vol. 863, 2005, p. 227 provides an investigation of thermal oxidation of Cu interconnects including a CoWP cap. It is reported herein that CoWP is not a good barrier from thermal oxidation since it destroys the Cu interconnect.
Moreover, although the deposition of CoWP utilizing an electroless process is selective to the Cu-containing features, metal particles are formed on the surface of the dielectric material that is between the Cu-containing features. The presence of the metal particles or residues between the conductive features leads to high leakage currents (the leakage with CoWP is about ten times or higher compared to similar structures with no CoWP) and poor reliability.
In view of the above, there is a need for providing a metal cap for a conductive feature which does not increase the leakage current of the interconnect structure, while avoiding the drawbacks mentioned in the Gambino et al. reference mentioned above.